About 65% of the Final will focus on the material since the last test, and about 35% will focus on the assembly language programming material from Test 2.
Chapter 6. (6.1-6.4) Processor Organization
Number of Addresses: Three-address, two-address, accumulator, stack machines
Load and store Architectures
Control Flow: conditional and unconditional branches; procedure calls and parameter passing
Instruction set design issues: operand types, addressing modes, instruction types, ML formats
Chapter 14. (14.1-14.3) RISC
CISC vs. RISC - motivation and characteristics of each
RISC Design Principles: Simple operations, register-to-register operations, simple addressing modes, Use of large register files (register windows, fixed-length and simple ML formats)
Chapter 8. Pipelining and Vector Processing (Sections 8.1 - 8.6)
Instruction Pipelining: pipeline registers - purpose
Pipeline stalls/delay causes:
1) structural hazards/resouce conflicts (i.e., piece of hardware needed by several stages at the same time)
2) data/control hazards (i.e., need a value before it is calculated) and bypass signal paths/forwarding to minimize stalls
3) branch delays (i.e., fetch wrong instructions before you either know it is a branch instruction or the outcome of the branch is known)
Ways to reduce the branch penalty: static branch prediction by the compiler, delayed branch, and using BHT,Branch History Table
Advanced Architectures: superpipelining, superscalar, VLIW architectures
Instruction-level parallelism and its limitations due to write-read/RAW data dependencies, procedural dependencies, and resource conflicts.
Machine-level parallelism
Instruction-issue policies: In-order Issue with In-order Completion, In-order Issue with Out-of-Order Completion, and Out-of-Order Issue with Out-of-Order Completion
Dependencies: output (write-write/WAW) dependencies, antidependencies (read-write/WAR)
Instruction window, Register renaming, Tomasulo's algorithm