Computer Organization Lectures for Fall 2006
|
Lecture |
Date |
Topics |
Overheads |
Handouts |
|---|---|---|---|---|
|
Final |
12/12 (Tuesday) |
Final Examination: 3-4:50 PM in ITT 328 (normal classroom) |
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|
|
31 |
12/7 |
Review for Final |
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|
30 |
12/5 |
Virtual Memory (section 6.5) and Pipelining Processors (section 5.5) |
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|
29 |
11/30 |
Cache (section 6.1-6.4) |
|
|
|
28 |
11/28 |
Hardware Support for the Operating System sections 8.1-8.2 & I/O sections 7.1-7.4 |
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|
26 |
11/16 |
Take Test 2 |
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|
|
25 |
11/14 |
Review for Test 2 |
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|
24 |
11/9 |
Logical, Shift & Rotate Instructions |
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23 |
11/7 |
Insertion Sort MIPS Register Convention and Array Example |
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|
22 |
11/2 |
CalculatePowers MIPS Register Convention Example |
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21 |
10/31 |
MIPS Register Conventions |
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20 |
10/26 |
Run-time Stack |
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19 |
10/24 |
MIPS Assembly Language |
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|
17 |
10/17 |
More Ch 4: MARIE control unit, Intel x86, MIPS architectures |
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16 |
10/12 |
More of Ch 4: MARIE Assembly Language programming |
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|
|
15 |
10/10 |
More of Ch 4: Bus, Clock, I/O, Memory, Interrupts, MARIE introduction |
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|
14 |
10/5 |
RAM Memory, Ch 4 |
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|
13 |
10/3 |
Registers, Shift Registers, Register Files |
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|
12 |
9/28 |
TEST 1 |
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|
|
11 |
9/26 |
D-flip flop and register file and Review for Test 1 |
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|
10 |
9/21 |
One-bit memories: SR-latch, timing diagrams, gated/clocked SR-latch, D-latch |
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9 |
9/19 |
Combinational circuits: decoders, multiplexers, adders |
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7 |
9/12 |
Boolean logic |
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6 |
9/7 |
Character representation Error Detection and Correction |
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|
4 |
8/31 |
Floating Point Representation |
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3 |
8/29 |
Signed integers: two's complement |
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|
2 |
8/24 |
Computer History; unsigned numbers |
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|
1 |
8/22 |
Introduction to Computer Organization and Terminology |
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