Computer Organization Fall 2006

Lect #	Tuesday		Thursday
1	8/22	Ch 1: Computer components and terminology	8/24	Ch 1: History and von Neumann Model
3	8/29	2.1-2.3: Binary, Decimal, Hexadecimal numbers	8/31	2.4: Signed Integers
5	9/5	2.5 Floating Point numbers	9/7	2.6-2.7: Characters, Error Detection and Correction
7	9/12	3.1-3.4: Boolean logic and gates	9/14	3.5, 3A.1-3A.7: Kmaps and Combinational circuits
9	9/19	3.6: Clock, SR-latch, Flip-Flops	9/21	3.6-3.7: Sequential Circuits
11	9/26	4.1-4.3: Marie and review	9/28	Test 1
13	10/3	4.4-4.7: Clock, I/O, Memory, Interrupts	10/5	4.8-4.10: Marie Assembly Language
15	10/10	4.11-4.12: Assemblers and instruct set	10/12	4.13-4.14: Control Unit, Intel, and MIPS Instruction Sets
17	10/17	5.1-5.4: Instr. Set Architectures	10/19	5.5: Instruction-level Pipelining
19	10/24	5.6: Real-world ISAs	10/26	6.1-6.3 Memory Hierarchy
21	10/31	6.4: Cache	11/2	6.4: Cache
23	11/7	6.5: Virtural Memory	11/9	6.6: Real-world Memory Mgt.
23	11/14	7.1-7.4: I/O and review	11/16	Test 2
25	11/21	7.5-7.6: Data transmission and Disks	11/23	Thanksgiving Break
26	11/28	8.1-8.3: Operating System	11/30	Hardware support for the OS
28	12/5	8.4: Programming Tools	12/7	Review
Final: Tuesday, December 12 from 3-4:50 PM in ITT 328