Sample Final Questions over Material since Test 2
1. Suppose we had a block transfer from an I/O device to memory. The block consists of 1024 words and one word can be transferred at a time. For each of the following, indicate the number of interrupts needed to transfer a block:
b) interrupt-driven I/O
c) DMA (direct-memory access)
2. What is the main difference between programmed I/O and interrupt-driven I/O?
3. What is the main difference between interrupt-driven I/O and DMA?
4. Assume special I/O instructions are used to fill I/O-interface registers. Why can't a user program use these instructions to communicate with the I/O device directly and "by-pass" the operating system's protection checking?
5. Assume that memory-mapped I/O is used. Since Load and Store instructions are used to communicate with the I/O-interface registers, why can't a user program communicate with the I/O device directly and "by-pass" the operating system's protection checking?
6. Explain how a computer can protect against a user program going into an infinite loop.
7. Draw an output transfer timing diagram (similar to Figure 4.25) using multiple clock cycles for a synchronous bus.
8. What are the goals of the memory hierarchy on a computer system?
9. What are the advantages and disadvantages of dynamic RAM over static RAM?
10. Synchronous DRAM design allows for accesses in burst mode with 2 (or more) data transfers from consecutive memory addresses. Burst mode allows for faster access of the second and later data transfers. For example, Figure 5.9 has a 6-1-1-1 timing which means that the first data transfer require 6 bus cycles and the next three data transfers only require 1 bus cycle.
Why does the second through fourth data transfers take less time than the first data transf
11. Suppose we have a 32-bit address machine that is byte addressable. If it has a 128KB (217 bytes) cache with 64 (26) bytes per block.
a) How many total lines are in the cache?
b) If the cache is direct-mapped, how many cache lines could a specific memory block be mapped to?
c) If the cache is direct-mapped, what would be the format (tag bits, cache line bits, block offset bits) of the address? (Clearly indicate the number of bits in each)
d) If the cache is fully-associative, how many cache lines could a specific memory block be mapped to?
e) If the cache is fully-associative, what would be the format of the address?
f) If the cache is 4-way set associative, how many cache lines could a specific memory block be mapped to?
g) If the cache is 4-way set associative, how many sets would there be?
h) If the cache is 4-way set associative, what would be the format of the address?
12. A pipelined processor has a 128-KB split, Level-1 cache (two-way 64-KB data cache, and two-way 64-KB instruction cache). Why is a split, Level-1 caches usually used on pipeline processors?