Type of Instruction | ARM Assembly Language | Register Transfer Language Description |
Memory Access | LDR R1, Mem | R1 Mem (PC-relative; 32-bit operand) |
STR R1, Mem | MemR1 (PC-relative; 32-bit operand) | |
LDRB R1, Mem | R1 Mem (PC-relative; 8-bit operand) | |
STRB R1, Mem | MemR1 (PC-relative; 8-bit operand) | |
STMFD SP!, {R2-R4, LR} | Decrement SP by the size of the registers specified first, then mem[SP] R2, mem[SP+4] R3, ... , mem[SP+12] LR | |
LDMFD SP!, {R2-R4, PC} | First mem[SP] R2, mem[SP+4] R3, ... , mem[SP+12] PC, then increment SP by the size of the registers specified | |
STMFB, LDMFB, STMIB, STMFA, STMIA, STMEA, LDMDA, LDMFA, LDMIB, LDMED, STMEA, STMED, LDMIA, LDMEA (incr, decr, before, after, full, empty) | ||
Move | MOV R1, R2 | R1 R2 |
MVN R1, R2 | R1 not R2 | |
Arithmetic Instruction (reg. or immediate operands only) |
ADD R1, R2, R3 | R1 R2 + R3 |
SUB R1, R2, R3 | R1 R2 - R3 | |
MUL R1, R2, R3 | R1 (R2 x R3)[31:0] | |
ADC R1, R2, R3 | R1 R2 + R3 + C | |
SBC R1, R2, R3 | R1 R2 - R3 + C - 1 | |
RSB R1, R2, R3 | R1 R3 - R2 | |
RSC R1, R2, R3 | R1 R3 - R2 + C - 1 | |
Bit-wise Logical Instructions | AND R1, R2, R3 | R1 R2 and R3 |
ORR R1, R2, R3 | R1 R2 or R3 | |
BIC R1, R2, R3 | R1 R2 and (not R3) | |
ERR R1, R2, R3 | R1 R2 xor R3 | |
Comparison Instructions (set the condition codes, cc) |
CMP R1, R2 | Sets condition codes on R1 - R2 |
CMN R1, R2 | Sets condition codes on R1 + R2 | |
TST R1, R2 | Sets condition codes on R1 and R2 | |
TEQ R1, R2 | Sets condition codes on R1 xor R2 | |
Conditional Branch |
BGT LABEL | Branch to LABEL if condition codes are set for > |
BGE LABEL | Branch to LABEL if condition codes are set for >= | |
BLT LABEL | Branch to LABEL if condition codes are set for < | |
BLE LABEL | Branch to LABEL if condition codes are set for <= | |
BEQ LABEL | Branch to LABEL if condition codes are set for = | |
BNE LABEL | Branch to LABEL if condition codes are set for != | |
BPL LABEL | Branch to LABEL if condition codes are set for plus | |
BMI LABEL | Branch to LABEL if condition codes are set for minus | |
BVC LABEL | Branch to LABEL if no signed oVerflow (V=0) | |
BVS LABEL | Branch to LABEL if signed oVerflow set (V=1) | |
BCS LABEL | Branch to LABEL if condition code Carry is set | |
BCC LABEL | Branch to LABEL if condition code Carry is clear (0) | |
BHI LABEL | Branch to LABEL if unsigned comparison gave higher | |
BLS LABEL | Branch to LABEL if unsigned comparison gave lower or same | |
Unconditional Branch |
B LABEL or BAL LABEL |
Always Branch to LABEL |
BL LABEL | Branch to LABEL and Link (save return value to LR (R14)) |
1. Write an ARM assembly langage program to perform selection sort.
for (firstUnsorted = 0; firstUnsorted < n-1; firstUnsorted++) { minIndex = firstUnsorted; for (test = firstUnsorted+1; test <= n-1; test++) { if (a[test] < a[minIndex]) { minIndex = test; } // end if } // end for // Exchange smallest unsorted element with firstUnsorted temp = a[firstUnsorted]; a[firstUnsorted] = a[minIndex]; a[minIndex] = temp; } // end for
  | AREA MAIN, CODE, READONLY |
  | ENTRY |
  |   |
  |   |
  |   |
  | AREA DATA |
N | DCD 5 |
A | DCD 33, 6, 10, 5, 1 |
POINTER | A |
  | END |