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1. For 4-bit unsigned numbers, when do we have overflow and get the wrong result during addition? (Hint: think about the carry bits into and/or out of the most-significant bit)

2. a) For 4-bit signed numbers, complete the following table about signed overflow:

Sign of Operands for addition Expected Sign
of Result
Wrong Sign
of Result
(indicates overflow)

Operand 1

Operand 2

+ +

+ - These two rows cannot cause
signed overflow in addition

- +

- -

b) For 4-bit signed numbers, when do we have overflow and get the wrong result during addition? (Hint: think about the carry bits into and/or out of the most-significant bit)

3. a) If R = 0 and S = 1, then what will be the output on Q and ?

b) Now, if S goes to a 0 value, what happens to the output on Q and ?

c) Complete the following timing diagram for the SR latch:

4. Complete the following timing diagram for the Master-Slave D flip-flop:

Sign of Operands for addition		Expected Sign of Result	Wrong Sign of Result (indicates overflow)
Operand 1	Operand 2	Expected Sign of Result	Wrong Sign of Result (indicates overflow)
+	+
+	-	These two rows cannot cause signed overflow in addition
-	+	These two rows cannot cause signed overflow in addition
-	-