Test 1 will be Thursday, Feb. 20, in class. It will be closed book and notes, except for one 8.5" x 11" sheet of paper with notes.
Digital Logic: Appendix A and Sections 6.1 and 6.2
Truth tables for the gates
Boolean algebra notations: sum-of-products
Combinational circuit design (no memory): 1) determine truth table for function, 2) using Karnaugh/K-maps to get minimized sum-of-products function, 3) draw implementation of minimized function (using gates)
Common combinational circuits: 1-bit Adders (half and full), ripple adder, faster carry-lookahead adders, decoder, and multiplexer (MUX).
Number of gate delays for a circuit.
Sequential Circuits (Memory): SR latch - know how it remembers (two stable
states, etc.), know how it changes states;
Gated/Clocked SR and D latches. Master-slave D Flip Flop; their characteristic tables
Timing diagrams for latches and Flip Flops
Register file - design and usage
Basic structure and functional units of a computer
Functional units: Input, CPU, Memory, Output, System bus
CPU components: control unit, ALU, regs., internal CPU interconnection
Performance: basic performance equation, clock rate, RISC vs. CISC, pipelining and superscalar operations
Chapter 2. Only section 2.1
Unsigned binary numbers
Signed number representation: sign bit and magnitude, one's complement, two's complement
Addition and subtraction of signed and unsigned numbers
Overflow in integer arithmetic