The final will be 3-4:50 PM on Tuesday, May 4 in Wright 8. You will get two-pages (front and back of both sheets) 8.5" x 11" "cheat sheets" of notes.

About 50% of the Final will focus on the material since the last test, and about 50% will focus on the material from tests 1 and 2.

Review topics covered since Test 2 are:

Chapter 5. System Buses

Bus interconnection: shared collection of wires with lines classified as data, addr., control

Steps of a typical bus transfer

Bus design issues: 1) bus width, 2) bus type: dedicated/(time) multiplexed, 3) bus operations

Synchronous and asynchronous operations

Bus Arbitration: centralized vs. decentralized arbitration, Bus allocation policies, Bus release policies

Implementations of Dynamic Arbitration: Daisy-chaining, Independent requests, hybrid scheme

Multiple bus hierarchies

Chapter 19. Input/Output Organization

I/O Controller role and function

I/O address mapping: Isolated-I/O vs. memory-mapped I/O

I/O Data Transfer: programmed I/O, interrupt-driven I/O, and direct-memory access (DMA)

Error Dection and Correction: parity, Hamming code

Cyclic Redundancy Check (CRC)

External Interface: parallel vs serial, asynchronous vs. synchronous

Chapter 20. Interrupts

General interrupt mechanism

Usage of interrupts by the hardware/operating system to restrict a user program's activities