| Tuesday | Thursday | ||
| 1/13 | Chapter 1 | 1/15 | Ch 2: gates, SOP, algebraic simplification |
| 1/20 | Ch. 2 | 1/22 | Ch 3: Decoder, MUX, Comparators, Adders, ALU Appendix A: A.1 - A.3 |
| 1/27 | Ch 4.1 - 4.3 | 1/29 | Ch. 4.4 - 4.5.1 |
| 2/3 | Ch. 16.1-16.2; register-file design | 2/5 | 16.3-16.5; square-memory design |
| 2/10 | Appendix A: A.4 - A.6 | 2/12 | Appendix B |
| 2/17 | Ch. 6.1 - 6.2 | 2/19 | Ch 6.3 - 6.4 |
| 2/24 | Ch. 14 - 14.3 | 2/26 | Ch 15: MIPS arch |
| 3/2 | Review for test 1 | 3/4 | Test 1: Ch 1-4 & 16 |
| 3/9 | MIPS AL overview | 3/11 | Arrays |
| 3/16 | Spring Break | 3/18 | Spring Break |
| 3/23 | Ch 15 Reg. Conventions | 3/25 | |
| 3/30 | Ch 15 Logic and shift instr | 4/1 | |
| 4/6 | Ch 5.1 - 5.6.0 (buses) | 4/8 | |
| 4/13 | Review for Test 2 | 4/15 | Test 2 |
| 4/20 | Ch 19.1 - 19.6 (I/O) | 4/22 | |
| 4/27 | Ch 17.1 - 17.11 (cache) | 4/29 | |
| Finals: Tuesday, May 4 from 3-4:50 PM in Wright 8 | |||