Test 1 will be Thursday, February 24, in class. It will be closed book and notes, except for one 8.5" x 11" sheet of paper (front and back) with notes.

**Chapter 1. **

Basic structure and functional units of a computer

Functional units: Input, CPU, Memory, Output, System bus

CPU components: control unit, ALU, regs., internal CPU interconnection

**Digital Logic: Chapters 2, 3**

Truth tables for the gates

Boolean algebra notations: sum-of-products

Combinational circuit design (no memory): 1) determine truth table for function, 2) using Karnaugh/K-maps to get minimized sum-of-products function, 3) draw implementation of minimized function (using gates)

Common combinational circuits: 1-bit Adders (half and full), ripple adder, faster (2-bit) carry-lookahead adders, decoder, and multiplexer (MUX).

Number of gate delays for a circuit.

Complexity number of a circuit (# of gates + # inputs to gates)

**Register File and Memory: Chapters 4.1-4.5.1, 16.1-16.5**

Sequential Circuits (Memory): SR latch - know how it remembers (two stable

states, etc.), know how it changes states;

Gated/Clocked D latches. Master-slave D Flip Flop; their characteristic tables

Timing diagrams for latches and Flip Flops

Register file - design and usage

Square-memory implementation of large memories - understand (1) how the two level decoding of an address reduces the overhead for decoding, (2) how the tri-state buffers eliminate the need for MUXs, and (3) how a single-port RAM memory and two-level decoding reduces the wires to the memory chip

**Appendix A**

Unsigned binary numbers

Conversion between base 10, base 2, and base 16

Signed number representation: sign bit and magnitude, one's complement, two's complement, and excess-M

Addition and subtraction of signed and unsigned numbers

Overflow in integer arithmetic

Floating-point Representation: 32-bit and 64-bit IEEE 754 standard and special values

Addition and multiplication of floating-point numbers

**Appendix B**

Character representation in ASCII and Unicode