Computer Organization Spring 2005
Tuesday | Thursday | ||
1/11 | Chapter 1 | 1/13 | Ch 2: gates, SOP, algebraic simplification |
1/18 | Ch. 2 | 1/20 | Ch 3: Decoder, MUX, Comparators, Adders, ALU Appendix A: A.1 - A.3 |
1/25 | Ch 4.1 - 4.3 | 1/27 | Ch. 4.4 - 4.5.1 |
2/1 | Ch. 16.1-16.2; register-file design | 2/3 | 16.3-16.5; square-memory design |
2/8 | Appendix A: A.4 - A.6 | 2/10 | Appendix B |
2/15 | Ch. 6.1 - 6.2 | 2/17 | Ch 6.3 - 6.4 |
2/22 | Review for test 1 | 2/24 | Test 1: Ch 1-4 & 16 |
3/1 | Ch. 14 - 14.3 | 3/3 | Ch 15: MIPS arch and MIPS AL overview |
3/8 | Arrays | 3/10 | Ch 15 Reg. Conventions |
3/15 | Spring Break | 3/17 | Spring Break |
3/22 | MIPS AL Examples and Practice | 3/24 |   |
3/29 | Ch 15 Logic and shift instr | 3/31 |   |
4/5 | Review for Test 2 | 4/7 | Test 2 |
4/12 | Ch 5.1 - 5.6.0 (buses) | 4/14 |   |
4/19 | Ch 19.1 - 19.6 (I/O) | 4/21 |   |
4/26 | Ch 17.1 - 17.11 (cache) | 4/28 |   |
Finals: Thursday, May 5 from 10-11:50 AM in Wright 105 |