100112 +101102 |
1011012 +1101112 |
2. Complete the Full-Adder truth table for the sum (si) and carry-out (ci+1) functions.
xi |
yi |
carry-in ci |
sum si |
carry-out ci+1 |
0 | 0 | 0 |   |   |
0 | 0 | 1 |   |   |
0 | 1 | 0 |   |   |
0 | 1 | 1 |   |   |
1 | 0 | 0 |   |   |
1 | 0 | 1 |   |   |
1 | 1 | 0 |   |   |
1 | 1 | 1 |   |   |
3. Use k-maps to minimize the sum (si) and carry-out (ci+1) functions of the Full-Adder:
4. For the one-bit Full-Adder, how many gate delays are needed before the carry-out (ci+1) wire is correct?
5. A 32-bit, ripple-adder is made up of a collection of single-bit Full-Adders connected together as shown below:
How many gate delays are needed before c32 is correct?
6. To speed up the calculation of the carry-out (Ci+1) signals, consider constructing a 32-bit adder using two-bit adders as shown in:
If ci+1 is calculated directly from the inputs as c i+1 = xi yi + xi xi-1 yi-1 + xi xi-1 ci-1 + xi yi-1 ci-1
+ yi xi-1 yi-1 + yi xi-1 ci-1 + yi yi-1 ci-1, then how many gate delays would be needed to calculate the ci+1 signal in a two-bit adder?
7. What would be the total number of gate delays in a 32-bit adder before the c 32 signal is generated correctly if two-bit adders were used?
8. a) If R = 0 and S = 1, then what will be the output on Q and ?
b) Now, if S goes to a 0 value, what happens to the output on Q and ?