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1. How does a hierarchy of buses as shown in Figure 5.14 improve performance of a computer system?

2. What is the purpose of the "Bridge"s as shown in Figure 5.14?

3. In Figure 5.18 (write operation), why is a turn-around cycle not needed between the Address and Data on the AD lines?

4. (see next page)

5. In the PCI protocol each device has its own set of dedicated bus arbitration lines. All of the arbitration lines go to a centralized arbitrator. Why does the PCI protocol not specify a specific arbitration scheme (such as first-come-first-serve)?

4. Draw and explain a timing diagram for a PCI read operation (similar to Figure 5.19). Assume that 2 data transfers occur and that the following occurs during these transfers:

during the first data transfer the initiator is not ready for two clock cycles, and
during the second data transfer the target is not ready for one clock cycle.

On your diagram clearly indicate:

the address phase, data phase(s) and any wait states
which wire(s) are controlled by the target device and which are controlled by the initiator device
when the "target" reads the data off the bus