Advanced Architectures - multiple instructions completed per clock cycle

(Original RISC - one instruction completed per clock cycle)

  1. superpipelined (Figure 8.16)- split each stage into substages to create finer-grain stages
  2. superscalar (Figures 8.14 and 8.15)- multiple instructions in the same stage of execution in duplicate pipeline hardware
  3. very-long-instruction-word (VLIW) - compiler encodes multiple operations into a long instruction word so hardware can schedule these operations at run-time on multiple functional units without analysis
We looked at the Pentium, MIPS R4000, PowerPC, SPARC, and Vector processor examples from sections 8.6-8.7.