Computer Architecture Homework 5

Due: 10/29/04 (Friday)

Question 1. Use the handout on the register file to draw a complete (not just a one-bit slice) register file that has:

You can draw block-diagrams for flip-flops, decoders, and MUXs without showing their gate implementations.

Question 2. Suppose that we are implementing a 16 M x 8 (16M registers, each with 8 bits) register file with one write-port and one read-port.

a) How many and what type of decoder(s) would be needed?

b) How many total gates (assume up to 9-input (AND & OR) gates can be used) would be needed to implement this (these) decoder(s)?

c) How many and what type of MUX(s) would be needed?

d) How many total gates (assume up to 9-input (AND & OR) gates can be used) would be needed to implement this (these) MUX(s)?

e) Assuming D flip-flops to store each bit (5 gates/flip-flop). What % of the total gates is used to implement the D flip-flops?

Question 3. Redo the previous question using the 16 M x 8 square-memory implementation discussed in the class handout.

Question 4. Suppose we have 32-bit memory addresses, a byte-addressable memory, and a 512 KB (219 bytes) cache with 32 (25) bytes per block.

a) How many total lines are in the cache?

b) If the cache is direct-mapped, how many cache lines could a specific memory block be mapped to?

c) If the cache is direct-mapped, what would be the format (tag bits, cache line bits, block offset bits) of the address? (Clearly indicate the number of bits in each)

d) If the cache is 8-way set associative, how many cache lines could a specific memory block be mapped to?

e) If the cache is 8-way set associative, how many sets would there be?

f) If the cache is 8-way set associative, what would be the format of the address?

g) If the cache is fully-associative, how many cache lines could a specific memory block be mapped to?

h) If the cache is fully-associative, what would be the format of the address?