a) How many total lines are in the cache?
b) If the cache is direct-mapped, how many cache lines could a specific memory block be mapped to?
c) If the cache is direct-mapped, what would be the format (tag bits, cache line bits, block offset bits) of the address? (Clearly indicate the number of bits in each)
d) If the cache is fully-associative, how many cache lines could a specific memory block be mapped to?
e) If the cache is fully-associative, what would be the format of the address?
f) If the cache is 4-way set associative, how many cache lines could a specific memory block be mapped to?
g) If the cache is 4-way set associative, how many sets would there be?
h) If the cache is 4-way set associative, what would be the format of the address?