Test 1 for Computer Architecture will be Tuesday, Oct. 5 in class. The test will be closed book and notes, except for a single page of notes (8.5" x 11" front and back).

Chapter 1 and background:

High-level programming view: Run-time stack

Assembly-language programming:

Instruction/Machine cycle

Instruction-set Design Issues: which instructions to include (#, complexity), which built-in data types, instruction format [length (fixed, variable), number of address (2, 3, etc), field sizes],

# registers, addressing modes supported

Chapter 5. System Buses

Bus interconnection: shared collection of wires with lines classified as data, addr., control

Steps of a typical bus transfer

Bus design issues: 1) bus width, 2) bus type: dedicated/(time) multiplexed, 3) bus operations

Synchronous and asynchronous operations

Bus Arbitration: centralized vs. decentralized arbitration, Bus allocation policies, Bus release policies

Implementations of Dynamic Arbitration: Daisy-chaining, Independent requests, hybrid scheme

Multiple bus hierarchies

PCI bus protocol

Chapter 6. (6.1-6.4) Processor Organization

Number of Addresses: Three-address, two-address, accumulator, stack machines

Load and store Architectures

Control Flow: conditional and unconditional branches; procedure calls and parameter passing

Instruction set design issues: operand types, addressing modes, instruction types, ML formats

Chapter 14. (14.1-14.3) RISC

CISC vs. RISC - motiation and characteristics of each

RISC Design Principles: Simple operations, register-to-register operations, simple addressing modes, Use of large register files - register windows, fixed-length and simple ML formats

Chapter 8. Pipelining

General CPU organization: general purpose (user-visible) registers, control & status registers (PC, IR, MAR, MBR, PSW), ALU, control unit, internal CPU bus

Instruction cycle

Pipelining: pipeline registers - purpose

Pipeline stalls/delay causes:

1) structural hazards/resouce conflicts (i.e., piece of hardware needed by several stages at the same time)

2) data hazards (i.e., need a value before it is calculated) and bypass signal paths/forwarding to minimize

3) branch delays (i.e., fetch wrong instructions before you either know it is a branch instruction or the outcome of the branch is known)

Ways to reduce the branch penalty: branch prediction and delayed branch

Branch History Table

Performance Enhancements: superpipelining, superscalar, VLIW architectures

Superscalar characteristics

Instruction-level parallelism and its limitations due to write-read/RAW data dependencies, procedural dependencies, and resource conflicts.

Machine-level parallelism

Instruction-issue policies: In-order Issue with In-order Completion, In-order Issue with Out-of-Order Completion, and Out-of-Order Issue with Out-of-Order Completion

Dependencies: output (write-write/WAW) dependencies, antidependencies (read-write/WAR)

Instruction window, Register renaming, Tomasulo's algorithm