Test 2 will be Tuesday, Nov. 9, in class. You will be allowed a one-page (front and back) 8.5" x 11" "cheat sheet" of notes.

I've compiled a list of topics for the test, but I have not written the test yet.

Chapter 16. Memory System Design

Sequential Circuits (Memory): SR latch - know how it remembers (two stable

states, etc.), know how it changes states;

Gated/Clocked SR and D latches. Master-slave D Flip Flop; their characteristic tables

Register file - design and usage

Square-memory implementation of large memories

fast page-mode of Synchronous DRAM

static vs. dynamic

Chapter 17. Cache Memory

Motivation for cache: performance issues, Locality of reference (temporal and spatial)

Types of cache: direct mapped, fully associative, set associative

Replacement policies: random, FIFO, LRU

Write policies: write-through, write-back; cache-coherency solutions;

Types of cache: unified vs. split cache (separate instruction and data caches), number/level of caches, virtual vs. physically tagged caches

Pentium and PowerPC examples

Cache design issues: cache capacity, cache line size, degree of associativity

Chapter 18. Virtual Memory

General idea of the memory hierarchy

Virtual memory Concepts: pages, page frames, page faults, demand paging

Paging: page table, virtual to physical address translation, time and memory efficiency considerations, page-replacement policies and there implementations, write policy; page-size tradeoff,

Page Table Organization and Page table entries (physical page #, disk page address, valid bit, dirty bit, reference bit, owner information, protection bit)

TLB (translation lookaside buffer)

Page-table Placement: searching hierarchical page tables, inverted page table

frame-allocation algorithm: page-fault frequency

Segmentation

Combining paging and segmentation

Pentium processor memory-management example