Computer Architecture

Homework #5 Due: 12/2 (F)

Chapter 18: Exercises: 18-13, 18-20, 18-21, and the following exercises

1. Consider the demand paging system with 1024-byte pages.

a) Complete the above page table for Process A.

b) If process A is currently running and the CPU generates a logical/virtual address of 310810, then what would be the corresponding physical address?

2. For a paged memory system with a TLB (translation-lookaside buffer) and an L1 cache, what steps would be in the fastest memory access assuming that the L1 cache is tagged with physical memory addresses?

3. For a paged memory system with a TLB (translation-lookaside buffer) and an L1 cache, what steps would be in the fastest memory access assuming that the L1 cache is tagged with virtual addresses?

4. To approximate the LRU page-replacement algorithm most hardware supports the updating/setting of a reference bit (R-bit) in the page-table entry corresponding to each memory reference. To get a better approximation of LRU, additional counter/history bits can be maintained. Periodically, say every 20 milliseconds, the process is interrupted so the OS can shift the R-bit into the counter/history bits for each page-table entry and clear the R-bits. Such as

a) If the pages in main memory have the below R-bit and counter/history bits, then which page should be selected for replacement on a page fault?

b) If the R-bits are shifted every 10 milliseconds and R-bits are about to be shifted because the interrupt just occurred, how long (specify a range) has it been since page 3 was referenced?

5. Consider the following performance curve that is expected for a paged memory system.

Explain the shape of each section indicated on the above curve:

a) (rising part of the curve)

b) (falling part of the curve)

c) What should the operating system do if it detects that thrashing (the falling part of the curve) is occurring?