1. Consider the demand paging system with 1024-byte pages.

a) Complete the above page table for Process B.

b) If process B is currently running and the CPU generates a logical/virtual address of 103210, then what would be the corresponding physical address?

2. How does a TLB (translation-lookaside buffer) speed the process of address translation?

3. Blocks in the L1 cache can be tagged with physical/actual memory addresses, or by virtual addresses. What would be the advantage of having blocks in the L1 cache be tagged with virtual addresses?