Test 2 will be Tuesday, Nov. 15, in class. You will be allowed a one-page (front and back) 8.5" x 11" "cheat sheet" of notes.

I've compiled a list of topics for the test, but I have not written the test yet.

Chapter 8. Pipelining (general pipeline material covered on the last test)

Ways to reduce the branch penalty: branch prediction and delayed branch

Branch History Table

Performance Enhancements: superpipelining, superscalar, VLIW architectures

Superscalar characteristics

Instruction-level parallelism and its limitations due to write-read/RAW data dependencies, procedural dependencies, and resource conflicts.

Machine-level parallelism

Instruction-issue policies: In-order Issue with In-order Completion, In-order Issue with Out-of-Order Completion, and Out-of-Order Issue with Out-of-Order Completion

Dependencies: output (write-write/WAW) dependencies, antidependencies (read-write/WAR)

Instruction window, Register renaming, Tomasulo's algorithm

Chapter 16. Memory System Design

Sequential Circuits (Memory): SR latch - know how it remembers (two stable

states, etc.), know how it changes states;

Gated/Clocked SR and D latches. Master-slave D Flip Flop; their characteristic tables

Register file - design and usage

Square-memory implementation of large memories

fast page-mode of Synchronous DRAM

static vs. dynamic

Chapter 17. Cache Memory

Motivation for cache: performance issues, Locality of reference (temporal and spatial)

Types of cache: direct mapped, fully associative, set associative

Replacement policies: random, FIFO, LRU

Write policies: write-through, write-back; cache-coherency solutions;

Types of cache: unified vs. split cache (separate instruction and data caches), number/level of caches, virtual vs. physically tagged caches

Pentium and PowerPC examples

Cache design issues: cache capacity, cache line size, degree of associativity

Chapter 18. Virtual Memory (saved for the Final)