The Final will focus (60%) on the material since test 2, but there will be some comprehensive questions (about 20% from test 1 material and 20% from test 2 material) to see how well you understand the "big picture" of Computer Architecture as a whole.
Chapter 18. Virtual Memory
General idea of the memory hierarchy
Virtual memory Concepts: pages, page frames, page faults, demand paging
Paging: page table, virtual to physical address translation, time and memory efficiency considerations, page-replacement policies and there implementations, write policy; page-size tradeoff,
Page Table Organization and Page table entries (physical page #, disk page address, valid bit, dirty bit, reference bit, owner information, protection bit)
TLB (translation lookaside buffer)
Page-table Placement: searching hierarchical page tables, inverted page table
frame-allocation algorithm: page-fault frequency
Segmentation
Combining paging and segmentation
Pentium processor memory-management example
Chapter 19. Input/Output Organization
I/O Controller role and function
I/O address mapping: Isolated-I/O vs. memory-mapped I/O
I/O Data Transfer: programmed I/O, interrupt-driven I/O, and direct-memory access (DMA)
Error Dection and Correction: parity, Hamming code
Cyclic Redundancy Check (CRC)
External Interface: parallel vs serial, asynchronous vs. synchronous
General idea behind: USB, and to a less extent SCIS and IEEE 1394 (firewire)
Hard disks and RAID
General concepts of hard disk: seek time, rotational delay, data transfer time, layout of surfaces, tracks, and sector
RAID: levels, striping (bitwise to large stripes) effects on the number of independent requests that can be handled and the data transfer rate of a single large request.
Operation of RAID when a disk fails
I/O Performance Measures: throughput and response time
Chapter 20. Interrupts
General interrupt mechanism of the Pentium
Comparison of interrupts and procedures
Types of interrupts: software interrupt, hardware interrupt, exceptions
Maskable vs. nonmaskable interrupts
Usage of interrupts by the hardware/operating system to restrict a user program's activities
Steps involved when an interrupt occurs