Chapter 4. Performance:

Performance: throughput, response time, CPU execution time, user CPU time, system CPU time, clock cycle, clock rate, Instruction count, CPI

Process state diagram and OS queues

performance equation: CPU time = (Instruction count x CPI) / clock rate

Evaluating Performance: workload, SPEC benchmarks

Chapter 5. Processor: Datapath and Control:

General CPU organization: general purpose (user-visible) registers, control & status registers (PC, IR, MAR, MBR, PSW), ALU, control unit, internal CPU bus

Instruction cycle

Single-cycle implementation: datapath and control

multiple-cycle implementation: datapath and control, temporary registers (A, B, ALUOut, etc.)

performance comparison between single- and multiple-cycle implementations

Chapter 6. Pipelining

Instruction pipelining:

pipeline latches/registers - purpose

Pipeline stalls/delay causes:

1) structural hazards (i.e., piece of hardware needed by several stages at the same time)

2) data hazards (i.e., need a value before it is calculated) and bypass signal paths/forwarding to minimize

3) control hazards/branch delays (i.e., fetch wrong instructions before you either know it is a branch instruction or the outcome of the branch is known)

Ways to reduce the branch penalty: branch prediction, delayed branch, Branch Target Buffer

Superpipelining and Superscalar characteristics

Instruction-level parallelism and its limitations due to write-read/RAW data dependencies, procedural dependencies, and resource conflicts.

Machine-level parallelism

Instruction-issue policies: In-order Issue with In-order Completion, In-order Issue with Out-of-Order Completion, and Out-of-Order Issue with Out-of-Order Completion

Dependencies: true data dependencies (read-after-write/RAW), output (write-write/WAW) dependencies, antidependencies (read-write/WAR)

Instruction window, Register renaming, Tomasulo's algorithm, loop unrolling

static-multiple issue vs. dynamic-multiple issue