1) What type of messages (see Figure 6.28) should be sent by the home directory at P_i to

a) P_S and P_t:

b) P_j:

2) What should the state for the block containing address A be changed to? Shared, Uncached, or Exclusive

3) What processor(s) should be in the list of processors that have the block containing address A cached?

4) What type of messages (see Figure 6.28) should be sent by the home directory at P_i to

a) P_S and P_t:

b) P_j:

5) What should the state for the block containing address A be changed to? Shared, Uncached, or Exclusive

6) What processor(s) should be in the list of processors that have the block containing address A cached?

7) What type of messages (see Figure 6.28) should be sent and/or received by the home directory at P_i to

a) P_S

b) P_t:

c) P_j:

8) What should the state for the block containing address A be changed to? Shared, Uncached, or Exclusive

9) What processor(s) should be in the list of processors that have the block containing address A cached?

10) a) If cache coherence is supported for a multiprocessor, does the following code enforce synchronization?

DADDUI R2, R0, #1 ; R2 := 1

lockit: EXCH R2, 0 (R1) ; R1 points to "lock"

BNEZ R2, lockit ; branch if R2 Not Equal to Zero

b) If the above code enforces synchronization, how much cache coherence message traffic does it generate?