1) In Figure 5.3, which device (CPU or Memory) is driving the control wires:

a) I0/?

b) / write?

c) ?

2) Draw a Memory write operation with two wait states.

3) In Figure 5.7 (asynchronous read), how was bus skew handled?

4). Suppose we had a block transfer from an I/O device to memory. The block consists of 1024 words and one word can be transferred at a time. For each of the following, indicate the number of interrupts needed to transfer a block:

a) programmed-I/O

b) interrupt-driven I/O

c) DMA (direct-memory access)

5) What is the main difference between programmed I/O and interrupt-driven I/O?

6) What is the main difference between interrupt-driven I/O and DMA?

7) Assume special I/O instructions are used to fill I/O-controller registers. Why can't a user program use these instructions to communicate with the I/O device directly and "by-pass" the operating system's protection checking?

8) Assume that memory-mapped I/O is used. Since Load and Store instructions are used to communicate with the I/O-controller registers, why can't a user program communicate with the I/O device directly and "by-pass" the operating system's protection checking?