Chapter 6
Section 6.1
Taxonomy of Parallel Architectures: SISD, SIMD, MISD, MIMD
Memory organizations: centralized shared-memory and symmetric (shared-memory) multiprocessors (SMPs), and distributed-memory multiprocessors
Models for communication and memory architectures for multiprocessors: distributed shared-memory (DSM), message-passing multiprocessors (multicomputers/clusters)
Advantages of shared-memory communication and message-passing comunications
Challenges of parallel processing: limited parallelism of a program and high cost of communications
General idea of Amdahl's law
Section 6.2: Characteristics of Application Domains
There won't be much on the test directly related to this section, but I suggest you read it to get a feel for the type of benchmark applications.
Section 6.3 Symmetric Shared-Memory Architectures
Understanding of the general idea of multiprocessor cache coherence problem
Basic cache coherence schemes: directory based and snoopy
Performance of invalidate vs. write update snoopy protocols
Implementation of invalidate protocol (Figures 16.11 and Figures 16.12)
Section 6.4 Performance of Symmetric Shared-Memory Multiprocessors
general idea of coherence misses and false sharing
The details of the commercial workloads is not something I would expect you to remember.
Section 6.5 Distributed Shared-Memory Architectures
Directory-based cache-coherence protocol implementation
(Figures 6.28, 6.29, and 6.30)
Section 6.6 Performance of Distributed Shared-Memory Multiprocessors
Again, details are not something I expect you to remember.
Section 6.7 Synchronization
Synchronization on small SMP: spinlock using atomic exchange (bottom of page 593), load linked/store conditional primitives
Reasons that spin lock techniques don't scale up well: contention for lock and serialization of lock access
sense-barrier code (figures 6.38 and 6.39)
Synchronization mechanisms for large-scale multiprocessors: software implementations (spinlock with exponiential backoff, queuing locks, and combining tree), and hardware implementations (queuing locks)
Section 6.8 Models of Memory Consistency: An introduction
general problem idea
Sequential consistency