The final will be 8-9:50 AM on Tuesday, Dec. 16 in Wright 8. You will again get a one-page (front and back) 8.5" x 11" "cheat sheet" of notes.

The Final will focus on the material since the last test. However, I might ask some "big picture" comprehensive questions which do not expect you to know the details from the previous two tests. These questions will only amount to 10% of the final exam.

Chapter 7. Storage Systems (sections 7.1 - 7.7 with an emphasis on 7.2, 7.3, 7.5)

Types of Storage Devices with a focus on magnetic disks

Bus interconnection: shared collection of wires with lines classified as data, address, and control

Steps of a typical bus transfer

Bus design issues: 1) bus width, 2) bus type: dedicated/(time) multiplexed, 3) bus operations

Synchronous and asynchronous operations

Bus skew

Bus Arbitration: centralized vs. decentralized arbitration

Implementations of Dynamic Arbitration: Daisy-chaining, Independent requests, hybrid schemes

Interfacing Storage Devices to the CPU:

I/O module operation and function

I/O instructions: memory-mapped I/O and isolated I/O

I/O techniques: programmed I/O, interrupt-driven I/O, and direct-memory access (DMA)

Reliability, Availability, and Dependability terminology and usage

RAID: levels, striping (bitwise to large stripes) effects on the number of independent requests that can be handled and the data transfer rate of a single large request.

Operation of RAID when a disk fails

I/O Performance Measures: throughput and response time

Appendix A. Pipelining

Instruction Pipelining: pipeline registers - purpose

Pipeline stalls/delay causes:

1) structural hazards/resouce conflicts (i.e., piece of hardware needed by several stages at the same time)

2) data hazards (i.e., need a value before it is calculated) and bypass signal paths/forwarding to minimize stalls

3) branch delays (i.e., fetch wrong instructions before you either know it is a branch instruction or the outcome of the branch is known)

Ways to reduce the branch penalty: branch prediction and delayed branch

Branch History Table

Chapter 3. Instruction-level Parallelism (emphasis on Sections 3.1-3.4)

Advanced Architectures: superpipelining, superscalar, VLIW architectures

Instruction-level parallelism and its limitations due to write-read/RAW data dependencies, procedural dependencies, and resource conflicts.

Machine-level parallelism

Instruction-issue policies: In-order Issue with In-order Completion, In-order Issue with Out-of-Order Completion, and Out-of-Order Issue with Out-of-Order Completion

Dependencies: output (write-write/WAW) dependencies, antidependencies (read-write/WAR)

Instruction window, Register renaming, Tomasulo's algorithm