HW #3 Computer Systems

Due: 3/14/02 (Th)

1. The asynchronous Read timing diagram of Figure 3.19 bothers me. I think that the "slave" should not issue the SSYN and Data Line signals at the same time during the start of the Read.

a) Describe why this might create a problem.

b) Propose a solution and draw a new timing diagram to fix this problem.

2. Draw and explain a timing diagram for a PCI write operation. Assume that 2 data transfers occur and that the following occurs during these transfers:

• during the first data transfer the target is not ready for two clock cycles, and
• during the second data transfer the initiator is not ready for two clock cycles.

• the address and data phases and any wait states,
• which wire(s) are controlled by the target device, initiator device, or both, and
• when the data is read off the bus by the target.

3. Draw and explain a timing diagram similar to Figure 3.24 assuming the followed:

• device A wants to do a write transfer of one piece of data at cycle 0
• device B wants to do a read transfer of one piece of data at cycle 0
• device C wants to do a read transfer of one piece of data at cycle 4
• the arbiter set the device priority as Device C > Device B > Device A