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HW #3 Computer Systems Solution

Due: 3/14/02 (Th)

1. The asynchronous Read timing diagram of Figure 3.19 bothers me. I think that the "slave" should not issue the SSYN and Data Line signals at the same time during the start of the Read.

a) Describe why this might create a problem.

When the slave asserts the SSYN at the same time as Data lines, the master might read the Data lines before they have stabilized. (I.e., because of bus skew, the SSYN might arrive at the master before all the Data signals.) If the master reads immediately when the SSYN is asserted, it could read garbage off the Data lines.

b) Propose a solution and draw a new timing diagram to fix this problem.

One solution would be to have the master wait sufficiently long after seeing that the SSYN is asserted before it reads the Data lines. In this solution, the figure does not need to be modified, but this solution seems a little inconsistent with the way the MSYN is handled.

An alternate solution would be for the slave to send the Data after it sees the MSYN is asserted. The slave can wait until the Data lines have stablized before asserting the SSYN line. The start of the figure would then look like:

2. Draw and explain a timing diagram for a PCI write operation. Assume that 2 data transfers occur and that the following occurs during these transfers:

during the first data transfer the target is not ready for two clock cycles, and
during the second data transfer the initiator is not ready for two clock cycles.

You are to draw a diagram similiar to figure 3.22. On your diagram clearly indicate:

the address and data phases and any wait states,
which wire(s) are controlled by the target device, initiator device, or both, and
when the data is read off the bus by the target.

3. Draw and explain a timing diagram similar to Figure 3.24 assuming the followed:

device A wants to do a write transfer of one piece of data at cycle 0
device B wants to do a read transfer of one piece of data at cycle 0
device C wants to do a read transfer of one piece of data at cycle 4
the arbiter set the device priority as Device C > Device B > Device A

Assume that each transfer has only a single data phase and both the initiator and target are ready as soon as possible during the transfer.