Chapter 3.
Top-level view of computer: CPU, memory, I/O modules
Instruction cycle
Interrupts: types, goal, steps involved when an interrupt occurs
Interconnection structures: paths and types of exchange
Bus interconnection: shared collection of wires with lines classified as data, addr., control
Steps of a typical bus transfer
Types of buses: system bus, backplane bus, multiple bus hierarchies
Elements of bus design: 1) dedicated/(time) multiplexed, 2) centralized vs.
decentralized arbitration, 3) sychronous vs. asynchronous timing, 4) bus width
PCI bus protocol
Appendix A. Digital Logic
Common combinational circuits: decoder, multiplexer (MUX)
Sequential Circuits (Memory): SR latch - know how it remembers (two stable
states, etc.), know how it changes states;
Clocked Flip Flops: SR flip flop, D Flip flop, etc.; their characteristic tables
register file - design and usage
Chapter 4. Internal Memory
Key characteristics of memory - table 4.1
performance: access time, memory cycle time, transfer rate
Memory hierarchy: levels and goals (speed, capacity, and cost)
Locality of reference (temporal and spatial)
Idea of cache (and virtual memory)
Advanced DRAM Organizations: Enhanced DRAM, Cache DRAM, and Synchronous DRAM
RAM: static and dynamic
cache: type (direct mapped, fully associative, set associative); replacement
algorithms; write policies (write-through, write-back); cache-coherency solutions; block size; number/level of caches; unified vs. split cache
Pentium II and PowerPC examples