Computer Systems Test 2

Question 1. (7 points) Answer the following question about the SR-latch as shown below.

a) If R = 1 and S = 0, then what will be the output on Q and ?

b) Now, if R goes to a 0 value, what happens to the output on Q and ?

Justify your answer to part b.

Question 2. (8 points) Answer the following questions about a 4M (222) x 8 DRAM memory implemented as a square array.

a) How many and what type (#-to-#) of decoders would be needed?

b) Why is the 22-bit address split into < 11-bit "row" #, 11-bit "column" #> instead of < 11-bit "column" #, 11-bit "row #>?

Question 3. (10 points) All of the advanced memory RAMs, such as Enhanced Dynamic RAM (EDRAM) have a burst capability to allow multiple memory accesses faster that repeated accesses for scattered memory words.

a) Why is a burst feature useful for computers with a cache?

b) To reduce the CPU-idle time when a cache miss occurs, the word causing the miss can be fetched first from memory and supplied to the CPU. Therefore, the CPU can continue to operate while the remainder of the memory block is transferred to cache. How does the design of the Enhanced Dynamic RAM (see EDRAM diagram on the back page of the test) allow for this optimization?

Question 4. (15 points) Answer the following questions about the PCI Read diagram above:

a) When does the initiator read the data off the AD wires?

b) When is the initator not ready to read data?

c) When is the target not able to supply data?

d) How does the target know that it can stop supplying the first Data item?

e) How does the initiator know when data is on the AD wires?

f) When the initator deasserts the FRAME# wire during clock cycle 5, what is it "telling" the target?

Question 5. (5 points) What is the relationship between the length of the PCI bus and the duration of a clock cycle?

Question 6. (15 points) Suppose we have 32-bit memory addresses, a byte-addressable memory, and a 512 KB (219 bytes) cache with 32 (25) bytes per block.

a) How many total lines are in the cache?

b) If the cache is direct-mapped, how many cache lines could a specific memory block be mapped to?

c) If the cache is direct-mapped, what would be the format (tag bits, cache line bits, block offset bits) of the address? (Clearly indicate the number of bits in each)

d) If the cache is 2-way set associative, how many cache lines could a specific memory block be mapped to?

e) If the cache is 2-way set associative, how many sets would there be?

f) If the cache is 2-way set associative, what would be the format of the address?

g) If the cache is fully-associative, how many cache lines could a specific memory block be mapped to?

h) If the cache is fully-associative, what would be the format of the address?

Question 7. (10 points) What is the difference between the cache write policies: writeback and writethrough with respect to each of the following:

a) the relative frequency of memory accesses

b) the ability of a multiple CPU system to keep caches coherency