Test 1 for Computer Systems will be Thursday, Feb. 24 in class. The test will be closed book and notes, except for a single page of notes (8.5" x 11" front and back).

Chapter 10 and 11 and background:

High-level programming view: Run-time stack, Compiler, Linker

Assembly-language programming:

Addressing Modes: direct, immediate, register, register indirect, indirect, base-register, PC-relative, indexing

Instruction/Machine cycle

Instruction-set Design Issues: which instructions to include (#, complexity), which built-in data types, instruction format [length (fixed, variable), number of address (2, 3, etc), field sizes],

# registers, addressing modes supported

Chapter 12. CPU

General CPU organization: general purpose (user-visible) registers, control & status registers (PC, IR, MAR, MBR, PSW), ALU, control unit, internal CPU bus

Instruction cycle


pipeline registers - purpose

Pipeline stalls/delay causes:

1) structural hazards (i.e., piece of hardware needed by several stages at the same time)

2) data hazards (i.e., need a value before it is calculated) and bypass signal paths/forwarding to minimize

3) branch delays (i.e., fetch wrong instructions before you either know it is a branch instruction or the outcome of the branch is known)

Ways to reduce the branch penalty: multiple streams, prefetch branch of target, loop buffer, branch prediction, and delayed branch

Branch History Table

Chapter 13. RISC

CISC vs. RISC - motiation and characteristics of each

Use of large register files - register windows

register file vs. cache

Optimizations of pipeline - delayed branching and delayed load

Superpipelining - MIPS architecture

Sparc - register windows, cancelling conditional branches/annul bit

Chapter 14. ILP and Superscalar Processors

Superscalar characteristics

Instruction-level parallelism and its limitations due to write-read/RAW data dependencies, procedural dependencies, and resource conflicts.

Machine-level parallelism

Instruction-issue policies: In-order Issue with In-order Completion, In-order Issue with Out-of-Order Completion, and Out-of-Order Issue with Out-of-Order Completion

Dependencies: output (write-write/WAW) dependencies, antidependencies (read-write/WAR)

Instruction window, Register renaming, Tomasulo's algorithm

General understanding of the Pentium 4 pipeline (DON'T memory stages, but just try to get the general concepts)

Chapter 15. IA-64 / Itanium

Interesting Features:

* Uses explicit parallel instruction computing (EPIC) from very-long-instruction-word (VLIW) architecture.

* Provides hardware support for efficient procedure calls and returns via large number of registers with overlapping register windows

* Branch predication (NOT branch prediction) that allows speculative execution along both paths of a branch

* Speculative loading