Chapter 3. (Mostly Sections 3.3 to 3.7)

Bus interconnection: shared collection of wires with lines classified as data, addr., control

Steps of a typical bus transfer

Types of buses: system bus, backplane bus, multiple bus hierarchies

Elements of bus design: 1) dedicated/(time) multiplexed, 2) centralized vs.

decentralized arbitration, 3) sychronous vs. asynchronous timing, 4) bus width

PCI bus protocol

Appendix A. Digital Logic

Common combinational circuits: decoder, multiplexer (MUX)

Sequential Circuits (Memory): SR latch - know how it remembers (two stable

states, etc.), know how it changes states;

Clocked Flip Flops: SR flip flop, D Flip flop, etc.; their characteristic tables

register file - design and usage

Chapter 4. Cache Memory

Key characteristics of memory - table 4.1

Performance: access time, memory cycle time, transfer rate

Memory hierarchy: levels and goals (speed, capacity, and cost)

Locality of reference (temporal and spatial)

Idea of cache (and virtual memory)

cache: type (direct mapped, fully associative, set associative); replacement

algorithms; write policies (write-through, write-back); cache-coherency solutions; block size; number/level of caches; unified vs. split cache

Chapter 5. Internal Memory

RAM: static (SRAM) and dynamic (DRAM)

Square-memory design of RAM

Error Correction: single-error correction using Hamming Code,

Advanced DRAM Organizations: Synchronous DRAM (mainly), Rambus, and Cache DRAM