Date: Mon, 25 Feb 2008 15:37:37 -0600 (CST) From: Mark Jacobson To: 810-023-01-spring@uni.edu Subject: Quiz on Wednesday over Fetch/Execute cycle and Cache memory Hi 023 students, Wednesday quiz will be over the fetch/execute cycle and the Cache memory concepts we went over in class today. The fetch/execute cycle is: 1. fetch the instruction at memory address IAR or PC, i.e. fetch RAM(PC) 2. increment the IAR (also called the PC) 3. execute the instruction that has been fetched IAR = Instruction Address Register PC = Program Counter Two terms for the exact same thing, whatever register in the CPU that contains the address of the instruction that will next be FETCHed during the FETCH portion of the FETCH/Execute cycle. How does the IAR (or PC) get changed? Increment the IAR adds 1 to the Program Counter. Jump Instructions put a different number into the PC (the IAR) when they are EXECUTEd. JMP 200 would place the number 200 into the IAR, wiping out whatever was placed in there just before the JMP 200 instruction was EXECUTEd. ------ Let us imagine that instruction JMP 200 is located at RAM address 243. 1. Fetch RAM(IAR) The IAR contains address 243 JMP 200 is fetched from RAM(243) 2. Increment the IAR The IAR now contains 244 IAR = 243 + 1 = add one to IAR = 244 3. Execute (the JMP 200 instruction) IAR now has 200 instead of 244 Guess where the next instruction will be FETCHed from? address 200 of RAM, i.e. RAM(IAR) = RAM(200) address 244 does NOT get Fetched! --- --- Why did 244 NOT get fetched? Because of the EXECUTION of the JMP 200 instruction! 1. Fetch RAM(IAR) The IAR contains address 243 2. Increment the IAR The IAR now contains 244 3. Execute (the JMP 200 instruction) IAR now has 200 How is the FETCH/EXECUTE CYCLE model of how a CPU works that was shown in class an oversimplification? Because it does not show that there is Cache memory. L1 cache is on the CPU microprocessor chip itself. L2 cache is between RAM and the CPU microprocessor chip. L1 is extremely fast, almost as fast as the CPU itself. L2 is very fast to access. RAM is very, very, very slow to access compared to the speed at which the CPU can execute instructions. No real computer fetches 1 instruction from RAM or 1 data items from RAM. A CPU manages the L1 and L2 cache memory so that: Whenever the CPU tried to fetch the instruction for a program and cannot find it in L1 cache or in L2 cache memory, it fetches hundreds of instructions from RAM into Cache memory, all the "nearby" instructions to the one that is needed are brought into L2 cache and a smaller portion of those are brought into L1 cache. Whenever the CPU tries to fetch some data (words or numbers or whatever) that is needed and does not find it in L2 or L1 cache, it fetches 100s and 1000s of nearby data items to the one it needs and quickly moves them all to L2 cache and moves some of them to L1 cache. A huge portion of the time that the CPU needs to fetch another instruction or needs to fetch another piece of data to be processed by an instruction, it will find it: 1. conveniently right on the CPU chip itself in L1 (level 1) cache. The CPU does NOT have to slow down and wait for the instruction or data! You only have a few kilobytes of L1 cache and it is very expen$$$$$$$$$$$$$ive and scarce. 2. or, if not found in L1 cache, finds it in L2 cache which is very, very, very fast. You have a Megabyte or a few Megabytes of L2 cache. It is quite co$$$$tly compared to regular RAM, but 100s and 1000s of times FASTER than RAM. 3. For well designed programs and computer systems, the CPU only has to go out to slow, slow, slow RAM a few times for every 100,000 times it finds the next instructions and data items already at least in L2 cache and very often in L1 cache. If the CPU caused only one instruction to be fetched and DOES NOT MOVE a bunch of nearby instructions, that instruction was in L1 cache!!!!!!! If the CPU does not find it in L1 cache, it likely only has to go to L2 cache to find the instruction it needs. It brings all nearby L2 instructions quickly over to the CPU chip and fits as many as possible into L1 cache right there on the SAME CHIP AS THE CPU itself. That is what L1 cache is! --------------------------- This concludes today's review of the group exercise and presentation of the CPU simulator with the: 1. very basic mistake in the Fetch/Execute Cycle it contained, and the 2. oversimplification of the CPU and RAM relationship that never shows the role of Cache memory and how that complicates the explaining of the Fetch/Execute cycle. The quiz on Wednesday will be a cinch if you review these notes with pen and pencil and previous class handouts and notes in hand. You generally can't get command of the ideas without writing them down and drawing pictures and explaining them in your own words. You certainly can't understand them as well as you potentially could without doing that. Mark